Advancing AI Computing With Optimized Matrix Multiplication Techniques With RISC-V CPU
summary
Presents a RISC‑V CPU customized extension that adds specialized matrix‑multiplication instructions for AI workloads, plus a Smart‑LSU for tiled load/store and a Zero‑Overhead Boundary Handler to cut configuration cycles. Describes design goals—scalability, portability, higher compute density and reduced memory bandwidth—and reports preliminary GeMM and Conv2D results (up to ~90% kernel loop MAC utilization and compute‑to‑memory ratio >9.6 via unrolling).
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