Boosting AI on Semidynamics RISC-V Cores with Custom Tensor Instr...
summary
Semidynamics extends the RISC-V Vector Extension with three custom tensor instructions that operate directly on the vector register file (no extra state, Linux-save/restore friendly) and accumulate at 32 bits. The VPU RTL runs on FPGA, exposes a C/C++ SDK, and scales T cores (T4–T32) with required memory bus widths; a T32 delivers 2 TOPS/GHz for bf16/int16/bf16-like formats. Matrix kernels hit >80–95% efficiency for sizes ~400–700, and a YOLOv3 demo reaches 33 fps for YOLOv3 at 1 GHz.
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chapters (7)
- 0:00Introduction and core design
- 1:50Tensor extensions approach
- 4:02Programming and instruction set
- 7:37Architecture and data flow
- 10:17Performance and scalability
- 12:33Real-world testing and results
- 14:41Conclusion and Q&A
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