Remote Development with SCRx-based SDK
summary
Syntacore demonstrates remote debugging of RISC‑V systems using the Syntacore SDK with gdbserver and standard toolchain components (GCC, GDB, QEMU) from a local VS Code session. The demo runs on an FPGA with a quad S37 (64‑bit) configuration, Linux 5.14, 4 GB RAM and 1 Gb Ethernet, shows fixing an uninitialized variable live and runs a multicore dining‑philosophers test over a cache‑coherent interconnect, all working end‑to‑end.
AI-written summary · about
chapters (5)
- 0:00Introduction to presentation
- 2:29Setting up the development environment
- 3:13Debugging a factorial program
- 7:02Dining philosophers demo
- 8:41Cintacore offerings summary
related talks
10mDebugging on Homogeneous and Heterogeneous Multicore SoCs w/ RISC V
10mDemo: Catapult Studio for the RTXM-2200 RISC-V CPU
11mDemo: Heterogeneous Multicore Debugging of RISC-V Cores in Complex Chips
11mHeterogeneous Multicore Debugging of RISC-V Cores in Complex Chips
11mDemo: Accelerating SW Development and Validation of RISC-V Based Designs
11mFGMT-RiscV running on an FPGA evaluation board with a live GDB debug session
14mExtending RISC-V with SCAIE-V
11mDriving SoC Innovation with Synopsys RISC-V Solutions
