Getting Started with RISC-V Custom Instructions
summary
Imperas uses instruction-accurate simulation and a custom-extension library to add RISC-V instructions, then profiles C code to prove benefit. A ChaCha20 encoder example runs on the simulator at 1.15 billion IPS, shows a hotspot drop from 21.35% → 14.71% after adding the extension, and reduces instruction count and simulated time. Models integrate with CI (15–20k tests), Eclipse debug and trace show new instructions and registers, and the flow includes line coverage and RISC-V compliance checks.
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chapters (7)
- 0:00Introduction
- 0:25Imperas and RISC-V ecosystem
- 1:46RISC-V architecture benefits
- 2:46Modeling methodology
- 5:31Optimization process
- 8:29Deployment and verification
- 9:28Tooling and conclusion
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