Demo: Andes ACE: Enabling Custom RISCV Instructions Safely

on YouTube ↗11m

" summary

Andes demonstrates a pipeline that takes a SystemC golden model, a small Verilog snippet, and simple metadata and outputs ACE integrated hardware plus toolchain collateral: automatic opcode assignment, an ISS functional model, GCC intrinsics, a generated testbench and extended RTL ready to drop into the CPU database. The demo claims sandboxed insertion so baseline RISC‑V remains compliant, supports scalar and vector custom ops (RISC‑V reserves four major custom opcodes), and verifies cycle‑by‑cycle with randomized stimulus.

AI-written summary · about

" chapters (3)

1. 0:00Introduction to Andes
2. 1:23Customizing RISC-V
3. 5:00Automating instruction design

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