Demo: Accelerate RISC-V Development with Tessent UltraSight-V

on YouTube ↗09m

" summary

Tessent UltraSight-V is an on‑chip IP plus host software stack for RISC‑V that delivers run control via GDB/OpenOCD, E-trace compression for tightly encoded instruction trace, and a DMA/USB path for fast memory code loads claimed to be 70 to 100x faster than standard GDB loads. It exposes printf‑style five‑instruction logging, cycle‑accurate retire timestamps for performance analysis, PCIe/AXI and JTAG access, UVM verification suites, and Trace32 compatibility.

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