Early RISC-V Software Verification with SIM-V

on YouTube ↗13m

" summary

A fast functional RISC‑V simulator claims 2.5× faster execution than state‑of‑the‑art solutions, runs full Linux systems and exposes the PMU so perf returns cycle and pagefault counts, and attaches to GDB and CLion for source‑level debugging. It ships an SDK to implement custom instructions and CSRs with a JIT backend, plugs into SystemC TLM (including a parallel TLM mode for multicore) and integrates via VCML into virtual platforms that scale into the cloud.

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" chapters (4)

1. 0:00Start
2. 0:19Virtual Prototyping
3. 4:25SIM-V Custom Extensions
4. 6:34Interoperability

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