Imperas Interview

on YouTube ↗06m

" summary

Imperas describes concrete work: a RISC‑V Imperas DV processor verification product line with new functional coverage verification IP for measurable verification metrics, plus partnerships with IP vendors SiFive Andes Codasip MIPS NSI Techs and EDA/test companies Cadence Mentor Synopsys Brecker and Valtrex. Reports adoption by Intel Qualcomm Marbella and Renaissance, notes ISO 26262 certification activity for Andes SiFive MIPS NSI tax, and timestamps milestones: six years in RISC‑V, five years to first paying customer, four years to a taped‑out RISC‑V SoC.

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