Keynote: Launchpad
Talkat RISC-V Summit North America 2024 · on Tuesday, 2024-10-22· at 16:30· Mission City Ballroom B2 - B5 (Level 1)·
summary
Eight two-minute pitches pack product claims and demos: Synopsys shows Fusion quick‑start kits, Imperas FPM/DV and Arc 5 IP for RTL, Aikana demos FPGA/Palladium silicon of out‑of‑order cores and a “20 48 bit” vector/AI extension, Andes unveils AX46 MPV scaling to 16 cores and widened vectors, Breer supplies 15 commercial RISC‑V projects worth of high‑coverage tests, Open Hardware cites 500 million cores shipped, HighFive P550 first 100 units selling fast, E4 presents a four‑node RISC‑V HPC prototype, SemiDynamics touts an out‑of‑order RVV 1.0 vector plus programmable tensor.
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chapters (11)
- 0:00Welcome to Launchpad
- 0:22Synopsys RISC-V support
- 3:15Aiana high-performance IP
- 6:10Andes RISC-V portfolio
- 8:23Breker verification solutions
- 10:28Kip processor customization
- 13:03E4 HPC with RISC-V
- 15:57Open Hardware Group cores
- 18:49SciFive RISC-V IP portfolio
- 20:55Semi Dynamics AI IP
- 23:24Closing remarks
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