RISC-V Summit North America 2024
2024-10-22..2024-10-23
Santa Clara, United States
[RISC-V Summit North America 2023, RISC-V Summit North America 2024, RISC-V Summit North America 2025]
as the organisers put it
REGISTER SPONSOR Submit to Speak VIEW THE AGENDA VIRTUAL EVENT ACCESS Thank you to all who joined us for RISC-V Summit 2024! We look forward to seeing you at future events. To experience the best of…
| title | author | length |
|---|---|---|
| An Adaptive Interrupt Architecture for Extremely Timing-Critical Applications | Jamie Kim | 19m |
A scalable interrupt microarchitecture duplicates most general-purpose registers and CSRs and adds a hardware preemption controller plus a per-interrupt lookup… | ||
| Exploring Real-Time Operating System Execution Strategies on Virtual Machines in RISC-V Architecture | Ryosuke Yamamoto | 20m |
Shows a concrete method to let RTOSes that assume Machine mode run inside a RISC‑V hypervisor: virtualize M‑mode instructions, provide virtual CSRs, trap… | ||
| RISC-V Needs More Secure “Wheels”! A Perspective for/from Automotive Industry | Thomas Roecker, Sandro Pinto | 19m |
Argues RISC-V needs richer isolation for zonal automotive ECUs, claiming WorldGuard’s current 32-ID limit (Xilinx 32-bit) won’t scale and realistic designs… | ||
| Lessons Learned in Using RISC-V for Generative AI and Where We Can Go from Here | Jayesh Iyer, Josep M Perez | 18m |
Generative AI workloads hit a memory and compute wall, so Esperanto builds RISC-V based inference accelerators and software that actually run open LLMs: EToc1… | ||
| Development of the First Open-Source Implementation of the RISC-V Vector Cryptography Extension | Markku-Juhani O. Saarinen | 23m |
Marian is the first open‑source implementation of the RISC‑V Vector Cryptography extension built on the PULP Ara2 core and validated on UltraScale FPGA with… | ||
| The Future of Mission Critical Edge Compute Is RISC-V | David Levy | 21m |
Mission-critical edge needs high-throughput MPUs with time-and-space partitioning, fault isolation, and redundancy; RISC-V delivers WorldGuard isolation (up to… | ||
| Berberis: Dynamic Binary Translation from RISC-V to X86_64 on Android | Lev Rumyantsev, Jeremiah Griffin | 17m |
Berberis translates riscv64 native libraries inside Android APKs to x86_64 at runtime, running only user code while the kernel, Android runtime and system… | ||
| Automotive Solution Empowered by RISC-V Based Security and Functional Safety Module | Jianying Peng | 16m |
Nuclei reports two ASIL‑D certified RISC‑V cores (NA900 then NA300), a safety‑aware bus fabric and a newly released RISC‑V HSM, with about 15+ automotive… | ||
| CPU Security in the Context of RISC-V | Karthik Raj Shekar | 18m |
Secure-IC describes an RTL Cyber escort unit that enforces CCFI and a secure call mechanism to block buffer overflows and detect control-flow tampering via a… | ||
| Bridging the Gap: Compiling and Optimizing Triton Kernels Onto RISC-V Targets Based on MLIR | Aries Wu | 34m |
An end to end stack lowers Triton kernels and PyTorch/ONNX/TensorFlow/JAX graphs into MLIR (linalg/tensor/vector/scf) and then LLVM to target RISC‑V, with a… | ||
| LLM Inference on RISC-V Embedded CPUs | Yueh-Feng Lee | 17m |
Optimizes LLaMA.cpp for the RISC-V P extension and runs TinyLLaMA 1.1B on an Andes Voyager board with a quad-core X45MP, using 8‑bit and 4‑bit quantization… | ||
| Building Tool Chains for RISC-V AI Accelerators | Jeremy Bennett | 19m |
A working open-source flow that runs PyTorch, TensorFlow and OpenXLA on an emulated RV64 accelerator using QEMU RISC‑V model of a few cores and a memory‑mapped… | ||
| The Benefits of Building New AI Accelerators with RISC-V | Cliff Young, Martin Maas | 45m |
Argues that RISC-V reduces risk and speeds new accelerator work by letting teams plug in custom units while keeping common register-based interfaces so IP… | ||
| Say Goodbye to Fear, Uncertainty, and Doubt: Innovate with Codasip Studio Fusion | Keith Graham | 17m |
Codasip Studio Fusion pairs formally verified L110/L730 cores with a workflow for bounded customization that adds custom instructions without breaking formal… | ||
| Driving the Future: Semiconductor Innovation, AI, and the Rise of RISC-V | Kelvin Low | 09m |
Samsung Foundry maps AI demand to concrete tech: GPT‑4 = 1.8T parameters, model size grows ~10×/year while AI hardware improves ~2–3×, and compute rose… | ||
| Demo: Super-optimized Ubuntu and Open Source on RISC-V | Gordan Markuš | 08m |
Canonical delivers Ubuntu builds for current RISC-V ISA (rv64/RVA20) across partner boards and reports shipping Ubuntu on the high five premier p550 (available… | ||
| Demo: Running Transformers on Semidynamic's "All-In-One" Vector and Tensor Unit | Roger Espasa | 11m |
Semidynamics runs Llama‑2 7B FP16 via ONNX Runtime on an R5‑controlled chip that integrates core, Vector and Tensor units with no external DMA. The Tensor unit… | ||
| Enhance the Performance of QEMU RVV Load/Store Implementation | Max Chou, Jeremy Bennett | 20m |
QEMU’s RVV loads/stores are a hotspot, so implementation uses per-page probing to pre-translate and validate pages once and then reuse translation and… | ||
| Applications and Explorations of RISC-V in the Field of Graphics Processing | Siqi Zhao | 12m |
Describes actual RISC-V RVV techniques applied to 2D graphics: uses segment load/store to load ARGB channels in one instruction, an RVV multiply-high… | ||
| From Momentum to Mainstream | Balaji Baktha | 05m |
Claims that Veron V2 is the first high‑performance data center RISC‑V CPU that bridges the x86/ARM performance gap, backed by a shipped chiplet system plus an… | ||
| Keynote: Empowering Innovation in Embedded Systems: Integrating AI, IoT and Edge Computing for Smarter Solutions | Patrick Johnson | 14m |
Microchip unveils PIC64 family specifics: the PIC64GX pentacore (quad cores plus monitor), the newly announced PIC64HX octal core up to 1 GHz, and built‑in… | ||
| Keynote: Leveraging RISC-V for All Computing Devices | Charlie Su | 16m |
Andes claims over 30% RISC‑V IP shipment market share and cites 2023 revenue growth of 2.8× with a projected ~15× to 2030. Roadmap highlights include the new… | ||
| Keynote: Co-Designing Software and Hardware: Pillars of Advancing RISC-V for Application Success | Xiaoning Qi | 15m |
XuanTie outlines concrete work: four CPU IPs open-sourced on GitHub, delivered 2 GHz SoCs for development, and ports of Android and commercial Linux variants… | ||
| Combined Dynamic and Formal Verification Approach to Processor Verification | Aimee Sutton, Xiaolin Chen | 21m |
Combines Synopsys tools and workflows to find more bugs faster: unit-level formal using VC Formal and assertion IP (AIP) exhaustively checks buffers, decoder… | ||
| Sail RISC-V: Status and Future Challenges | Alasdair Armstrong | 20m |
Sail is the RISC‑V golden model language with RV32/RV64 core, Vector and many Z extensions implemented, and a proof‑of‑concept for runtime configurability (no… | ||
| Keynote: Making RISC-V Real, Fast! | Yuning Liang, Nirav Patel | 20m |
DeepComputing and partners deliver working RISC‑V consumer hardware: a modular mainboard that becomes the first RISC‑V laptop and tablet, with two EVT… | ||
| Keynote: The Next Computing Megatrends are Enabled by RISC-V | Calista Redmond | 22m |
RISC-V claims measurable momentum: 2 billion SoCs shipped this year with forecasts to 20 billion SoCs in five years, market share rising from ~6% to over 25%… | ||
| Demo: XuanTie RISC-V Hardware and Software Full-stack Technology | James Shi | 14m |
Demonstrates XuanTie (Shen) full-stack IP: C-series C920/C930 application cores, R98 real-time automotive core, and E-series microcontroller, plus tooling that… | ||
| RISC-V CPU Development Using Olympia Performance Model | Knute Lingaard | 27m |
Describes using the Olympia performance model (C++), built on the Sparta framework, as a trace-driven simulator ingesting STF traces (examples: DRYSTONE). A… | ||
| Debug Signal Trace: HW Signal Capture in Post Silicon for Debug, Coverage and... | Sajosh Janarthanam | 18m |
Tenstorrent describes a hardware Debug Signal Trace (DST) that captures selected microarchitecture signals over many cycles and writes compressed packets to… | ||
| Keynote Panel: Powering Local Innovation and Global Success with RISC-V | Alessandro Campos, Jianying Peng, Roger Espasa, Ted Speers, Calista Redmond | 34m |
Panel argues that RISC-V moves from experiments to deployed systems: a NASA public‑private program selects an eight-core RISC-V vector processor for the High… | ||
| Demo: TraceLLM - Harness the Full Potential of your RISC-V Systems with an AI Based, Real-time, RISC-V Embedded Application Debug and Trace Analysis Engine | Rejeesh Shaji Babu | 11m |
TraceLLM integrates an LLM analysis engine with the RiscFree IDE and Ashling Vitra‑XS probe to capture non‑intrusive, real‑time traces and reconstruct full… | ||
| Demo: Securely Booting CHERI on a Full OS to Prevent Buffer Overflow Attacks | Carl Shaw | 11m |
Full RISC-V Linux boot replaces integer pointers across secure boot, OpenSBI, U-Boot, kernel and userland with capability-typed pointers on an FPGA bitstream… | ||
| Demo: Enabling Automotive Safety with Andes RISC-V IP | Marc Evans | 09m |
Andes RISC-V IP claims production-ready AAL D certified cores with the d45SE and d23SE released today and an out-of-order application core planned next year… | ||
| Load/Store Pair for RV32 (Zilsd & Zclsd) | Christian Herber | 19m |
Zilsd & Zclsd add RV32 load/store pair instructions by reusing RV64 doubleword encodings and compressed forms, allowing two-register aligned 64-bit accesses… | ||
| Keynote: Launchpad | Andrew Moore | 23m |
Eight two-minute pitches pack product claims and demos: Synopsys shows Fusion quick‑start kits, Imperas FPM/DV and Arc 5 IP for RTL, Aikana demos… | ||
| Keynote: Shaping the Future of Automotive Computing with RISC-V | Rich Collins | 11m |
Claims that RISC-V provides a single ISA from tiny body-electronics MCUs up to ADAS zonal controllers, and that real-time determinism needs custom extensions… | ||
| Keynote: RISC-V at NVIDIA: One Architecture, Dozens of Applications, Billions of Processors | Frans Sijstermans | 22m |
NVIDIA reports shipping 1–2 billion RISC‑V cores in 2024 with about 10–40 RISC‑V microcontrollers per chip, using a common hardware/software architecture that… | ||
| Demo: More Than Point Tools: RISC-V Solutions | Larry Lapides | 11m |
Synopsys presents a full RISC-V flow: formal model checking and assertion IP covering the ISA, dynamic verification with the Imperas FPM reference model… | ||
| Understanding the Unformated Trace & Diagnostic Data Packet Encapsulation for RI... | Iain Robertson | 18m |
Specification standardizes an encapsulation that already ratifies E‑Trace use and general unformatted diagnostics, and it ships a one‑byte header with a 5‑bit… | ||
| Keynote Panel: The Future of High Perfor... | Luisa Gonzalez, Nick Brown, Travis Lanier, Wei-han Lien | 40m |
RISC‑V is already powering diverse HPC experiments: TensTorrent cards and Thunderbird accelerators appear in demos, a Banana Pi runs AI workloads, and a claim… | ||
| Keynote Panel: The Future of... | Andrew Dellow, Kris Murphy, Pete Bernard, Pete Warden, Andrea Gallo | 30m |
Panel argues AI security needs hardware-to-cloud pipelines and shows concrete RISC‑V work: new extensions called Cove and coio to bind trusted sensors to… | ||
| Akeana : Breaking Performance Barriers | Graham Wilson | 13m |
Akeana presents RISC‑V IP claiming high throughput and production readiness: 25 SPECint for the 5000 family, a 32‑bit 100 series, midrange 1000 series, and a… | ||
| GPU Program Support on RISC-V GPU | Hyesoon Kim | 18m |
A usable stack that runs CUDA on CPUs and RISC-V combines an LLVM-based kernel transform pipeline with an open-source CUDA runtime and target-specific… | ||
| Software Simulation Is the Key to Success for Customized CPUs and Complex SoCs | Jon Taylor | 18m |
Argues that virtual platforms and fast golden processor models let teams evaluate custom RISC‑V instructions and system tradeoffs far faster than RTL, using… | ||
| SiFive Event Trace: The First Zero-Overhead Performance Tool for RISC-V Processors | Carsten Gosvig | 15m |
SiFive Event Trace is a hardware feature that injects call/return, exception, interrupt, watchpoint and trigger messages into the RISC-V ENTRACe stream so… | ||
| RISC-V Server SoC Standardization | Ved Shanbhogue | 16m |
A RISC-V server SoC specification defines concrete hardware requirements so a single binary OS image boots and runs across compliant systems. It mandates the… | ||
| Exploration of Productization of Android on RISC-V | Han Mao | 20m |
AOSP mainline RISC‑V work starts Sept 2022 and yields a board prototype and marketized standalone Android builds; JIT/AOT, Cuttlefish and many third‑party libs… | ||
| RISC-V LLVM State of the Union | Alex Bradbury | 17m |
Status update on RISC-V LLVM: LLVM supports the mandatory RV64G/23 extensions, has growing contributor diversity, and runs a CI-backed test farm using QEMU… | ||
| RISC-V Control-Flow Integrity (CFI) | Ved Shanbhogue, George Christou | 41m |
Ratified RISC‑V extensions Zicfiss (shadow stack) and Zicfilp (landing pads) provide concrete CFI: hardware shadow stacks with an SSP register and SS push/SS… | ||
| Software Engineers Are Tomorrow's Processor Engineers | Keith Graham | 17m |
RISC‑V plus Codasip tooling lets software engineers specify custom instructions using C‑like headers and codal files that generate opcodes and libraries, so… | ||
| Keynote: Instruction Sets Want to be Free - A 10 Year Retrospective | David Patterson | 14m |
Revisits the ten-year claim that an open ISA can evolve and scale, arguing evidence includes 400 organizations and 5,000 individual members, Berkeley’s eight… | ||
| Keynote: RISC-V State of the Union | Krste Asanovic | 21m |
RISC‑V announces RV23 ratified and mandates vectors and hypervisor for application processors, formalizing the jump from RVA20/RV64GC-era binaries to… | ||
| Demo: Introduction to Microchip's PIC64 Product Family and Demonstration of Video Pipeline on PIC64GX | David Levy, Battu Prakash Reddy | 18m |
Microchip launches a PIC64 family with a working video demo and clear specs: an 8-core HX with post-quantum crypto and integrated TSN switch, 240 GB/s switch… | ||
| RISC-V RAS Error-Record Register Interface (RERI) | Greg Favor | 19m |
RERI is a ratified register interface that standardizes per-component memory-mapped error registers grouped into configurable error banks with headers and… | ||
| RISC-V: Changing the Way AI/ML Accelerators and Computing Infrastructure Are Built | David Chen | 19m |
Stream Computing describes an AME matrix extension built as tile/block matrix instructions with an 8+8 register design, elemental-wise ops and RVV-decoupled… | ||
| Making the Case for a Keccak Instruction | Markku-Juhani O. Saarinen | 18m |
Proposes a dedicated Keccak/SHA3 instruction that packs the 1600-bit Keccak state across vector registers and an operand collector, showing the permutation… | ||
| Hardening Linux and FreeBSD on RISC-V with CHERI | Carl Shaw | 17m |
CHERI adds hardware capability pointers to RISC‑V so user and kernel memory accesses carry bounds, permissions and a hardware tag; FreeBSD already has spatial… | ||
| Keynote: RISC-V Security - Current Initiatives and Future Trends | Helena Handschuh | 16m |
Argues that secure AI-era platforms require a hardware root of trust, measured boot, trusted execution environments with hardware attestation, secure key… | ||
| Demo: Heterogeneous Multicore Debugging of RISC-V Cores in Complex Chips | Dennis Griffith | 11m |
Demo shows Lauterbach Trace32 controlling heterogeneous cores on a Zynq UltraScale+ MPSoC with four Cortex‑A53, two RISC‑V R5 and a MicroBlaze plus FPGA… | ||
| Demo: Andes ACE: Enabling Custom RISCV Instructions Safely | Darren Jones | 11m |
Andes demonstrates a pipeline that takes a SystemC golden model, a small Verilog snippet, and simple metadata and outputs ACE integrated hardware plus… | ||
| Simultaneous Multithreading with RISC-V Enables Higher Throughput Efficiency in Data-Centric Applications in Automotive | Vasanth Waran | 20m |
Claims a RISC‑V SMT core design for automotive sensor‑fusion and zonal/HPC use that ships in MIPS products and runs 2 or 4 hardware threads per core, targeting… | ||
| RISC-V Opportunities in Brazil | J. E.Bertuzzo | 14m |
Brazil names RISC-V a strategic platform and commits a $60 billion investment over three years for digital transformation, pairs RISC-V with AI to pursue… | ||
| RISC-V ACPI Is Ready for Server Platforms | Sunil V L, Himanshu Chauhan | 18m |
Three and a half years of specification work delivers a ready stack: ACPI updates land as ACPI 6.6, Linux 6.2 and QEMU 9.1 already carry patches, and EDK2 +… | ||
| Aggregation Optimization for SIMD Everywhere from ARM Neon to RISC-V Vector and Crypto Extensions | Jenq-Kuen Lee, Hung-Ming Lai | 19m |
Enhanced SIMDe headers provide direct ARM NEON→RVV and RISC‑V crypto mappings and land upstream, implemented as RVV intrinsics in LLVM IR. An LLVM pass called… | ||
| Keynote: Awards | Calista Redmond, Andrea Gallo | 06m |
Shivam Poar wins the hackathon with a submitted solution for the Tactical Computing Labs Challenge and receives a hardware prize from Deep Computing, the DC… | ||
| A Decade of Accelerating Adoption: RISC-V Market Analysis, From Now to 2031 | Rich Wawrzyniak | 26m |
SHD Group presents a market model projecting RISC‑V unit shipments to exceed 20 billion units by 2031, a 4 billion uplift from the prior 2030 estimate, with… | ||
| Keynote: Mobilizing the Open Source Software Ecosystem for RISC-V | Barna Ibrahim | 13m |
RISC‑V now runs Java 17/21/23/24 on RISC‑V, but major gaps remain: Python binary packages for key AI libraries are missing so developers must compile complex… | ||
| Hackathon Presentations | Megan Lane | 45m |
Students extend a RISC‑V CPU register file with real ECC prototypes using Codp Studio, trying Codp Studio register-file ECC with Hamming 38/32, 7‑4 Hamming and… | ||
| Demo: Accelerate RISC-V Development with Tessent UltraSight-V | Francisca Tan | 09m |
Tessent UltraSight-V is an on‑chip IP plus host software stack for RISC‑V that delivers run control via GDB/OpenOCD, E-trace compression for tightly encoded… | ||
| Open-Source Commercial-Grade RISC-V IOMMU with Verification | Manuel Sánchez Rodríguez, Saad Waheed | 19m |
Open-source, parameterizable RISC‑V IOMMU IP implements SV39 single and two‑stage translation, superpages, MSI translation modes, IO Address Translation… | ||
| Ratified N-Trace Specifications - an Overview | Robert Chyla, Jay Gamoneda | 19m |
Three ratified specs define a complete RISC-V trace stack: RISC-V N-Trace (Nexus based) for message formats and compression hooks, a Trace Control… | ||
| Collaboration Breakfast | David Patterson, Andrea Gallo, Nathan Egge, Amber Huffman | 38m |
Google hosts a software-focused breakfast about accelerating the RISC‑V ecosystem through Rise workgroups, upstream-first repos and cloud-access boards. Key… | ||
| Porting SLEEF to RISC-V | Ludovic Henry, Eric Love | 19m |
SLEEF gets a complete RISC‑V port that implements single, double and quad precision math plus a DFT backend, with RVV targets for LMUL=1 and LMUL=2 and… | ||
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