Jeremy Bennett
where else to find them
no profile links on file
what they talk about
all 7 in the filters
where they keep going back
no series more than once — all 5 in the filters
on a stage with
- Max Chouonce
who talks about the same things
nobody close enough yet
| title | conference | date |
|---|---|---|
| How to: Bringing up ExecuTorch on a RISC-V Microcontroller | Corrected Audio | RISC-V Summit Europe 2026 Developer Workshops | 2026-06-08 |
Step‑by‑step work to run ExecuTorch (PyTorch for embedded) on a bare‑metal RISC‑V microcontroller using a Verilator model of the OpenHW CV32E40Pv2 core, adding… | ||
| How to: Bringing up ExecuTorch on a RISC-V Microcontroller | RISC-V Summit Europe 2026 Developer Workshops | 2026-06-08 |
SPEAKER: Jeremy Bennett - Embecosm
This session was a part of the Software track at the RISC-V Developer Workshops held at RISC-V Summit Europe 2026 in… | ||
| Building Tool Chains for RISC-V AI Accelerators | RISC-V Summit North America 2024 | 2024-10-22 |
A working open-source flow that runs PyTorch, TensorFlow and OpenXLA on an emulated RV64 accelerator using QEMU RISC‑V model of a few cores and a memory‑mapped… | ||
| Enhance the Performance of QEMU RVV Load/Store Implementation | RISC-V Summit North America 2024 | 2024-10-22 |
QEMU’s RVV loads/stores are a hotspot, so implementation uses per-page probing to pre-translate and validate pages once and then reuse translation and… | ||
| Open Source Compiler Tool Chains for RISC V Past, Present and Future | RISC-V Summit 2019 | 2019-12-09 |
RISC‑V compiler work is usable but uneven: GCC is more mature (out‑of‑tree since 2011) while LLVM reached mainline recently and gained RV64 support in… | ||
| The role of software in validating silicon IP | Week of Open Source Hardware 2019 | 2019-06-13 |
Claims that software-only validation missed 13 missing instructions in OpenRISC when the compiler never emitted them, prompting a full UVM analysis; hybrid… | ||
| GDB for RISC-V: Extending Support for Bare Metal Multi-core Debugging | 8th RISC-V Workshop Barcelona 2018 | 2018-05-07 |
GDB has basic bare-metal RISC‑V support upstream since 6 March, providing register/memory access, start/stop and ABI-aware unwinding; testing shows a better… | ||
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