RISC-V Summit Europe 2026 Developer Workshops
2026-06-08
Bologna, Italy
[RISC-V Summit Europe 2023, RISC-V Summit Europe 2024, RISC-V Summit Europe 2025, RISC-V Summit Europe 2026, RISC-V Summit Europe 2026 Developer Workshops]
| title | author | length |
|---|---|---|
| Advanced Debug and Trace Tools for RISC-V Architectures | Maurizio Menegotto | 02h 00m |
Lauterbach demonstrates TRACE32 connected to a Microchip PolarFire SoC with an UltraSoC encoder and an FPGA AXI-to-PTI wrapper on GitHub that converts on‑chip… | ||
| From Open Silicon to Real Hardware: Hands-On RISC-V Development w/ Zephyr and Puppy Microcontroller | Marcelo Knörich Zuffo, Laisa Costa De Biase | 01h 10m |
Brazil’s Puppy is a PULPissimo-derived RISC‑V microcontroller running up to 100 MHz with crypto and AI acceleration, delivered as open‑source hardware and… | ||
| UCAgent: An End-to-End Agent for Unit-Level Chip Verification | Junyue Wang | 51m |
UCAgent builds a Python-first verification flow that avoids generating SystemVerilog directly by wrapping RTL with picker and toffee, decomposes verification… | ||
| Introduction to RISC-V in gem5 | Ivan Fernandez Vega | 58m |
Hands-on use of gem5 Standard Library to build a RISC-V board inside a Docker prebuilt environment, run GMEM benchmark with RVV, and collect stats, traces and… | ||
| Building an AI Accelerator with High-Level Synthesis | Werner Bachhuber | 53m |
A RISC‑V co‑processor for wake‑word inference is implemented from C++ using High‑Level Synthesis (Catapult) and integrated via AXI into a Rocket Core SoC… | ||
| Hands-on OP-TEE with Andes RISC-V | Paul Shan-Chyun Ku | 39m |
60-minute hands‑on workshop walks through three labs that demonstrate a real OP-TEE-on-RISC‑V build using Andes tooling and a Windows QEMU setup. Lab 1 creates… | ||
| How to: Bringing up ExecuTorch on a RISC-V Microcontroller | Corrected Audio | Jeremy Bennett | 56m |
Step‑by‑step work to run ExecuTorch (PyTorch for embedded) on a bare‑metal RISC‑V microcontroller using a Verilator model of the OpenHW CV32E40Pv2 core, adding… | ||
| Zephyr RTOS Debugging and Performance Analysis | Benjamin Cabé, Maurizio Menegotto | 57m |
Shows end-to-end setup and verification: Zephyr builds, flashes, and runs on a Microchip PolarFire SoC evaluation board, with TRACE32 PowerTrace attached to… | ||
| Hands-on TinyML Deployment on RISC-V: Building an Optimized Edge AI Pipeline - Corrected Audio | Niraj Dengale, Yueh-Feng Lee | 40m |
Hands-on pipeline shows model-to-firmware flow using NN Pilot and Andes compute libraries to map TinyML (Visual Wake Word / MLPerf Tiny) onto the RISC‑V vector… | ||
| Porting SIMD to RISC-V Vectors | Corrected Audio | Daniel Thompson | 01h 45m |
Claims RISC-V Vector (RVV) matches modern SIMD: 32 vector registers, hardware VL between 128 bits and 64K, and support for predication, scatter/gather and… | ||
| Building a Multi‑Guest Virtualized System with Bao on CVA6 in Automotive | Joerg Seitter, Sandro Pinto | 01h 01m |
Hands‑on build of a multi‑guest system on a CVA6 (MCU, no MMU) using the Bao hypervisor, QEMU/docker flows and FPGA bitstreams; the workshop implements CVA6… | ||
| Hands-on TinyML Deployment on RISC-V: Building an Optimized Edge AI Pipeline | Niraj Dengale, Yueh-Feng Lee | 40m |
Hands-on workshop shows a full pipeline that converts TinyML models to tuned binaries and runs them on RISC-V hardware using an open RISC-V AI software stack… | ||
| Porting SIMD to RISC-V Vectors | Daniel Thompson | 01h 45m |
SPEAKER:
Daniel Thompson, RISCstar Solutions
This session was a part of the Software track at the RISC-V Developer Workshops held at RISC-V Summit Europe 2026… | ||
| RISC-V Architectural Certification Tests Early Adoption Workshop | David Harris, Jordan Carlin | 53m |
Early-release RISC-V certification tooling generates self-checking assembly tests from a CSV/UDB-driven plan, uses sail as the reference model, produces… | ||
| How to: Bringing up ExecuTorch on a RISC-V Microcontroller | Jeremy Bennett | 56m |
SPEAKER: Jeremy Bennett - Embecosm
This session was a part of the Software track at the RISC-V Developer Workshops held at RISC-V Summit Europe 2026 in… | ||
| Hands-on Introduction to CHERI | Alfredo Mazzinghi, Marno van der Maas, John Thomson | 01h 33m |
Hands‑on workshop demonstrates CHERI capability pointers on a real Sonata FPGA board using chariot RTOS and an LLVM toolchain that produces UF2 images… | ||
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