Niraj Dengale
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| title | conference | date |
|---|---|---|
| Hands-on TinyML Deployment on RISC-V: Building an Optimized Edge AI Pipeline - Corrected Audio | RISC-V Summit Europe 2026 Developer Workshops | 2026-06-08 |
Hands-on pipeline shows model-to-firmware flow using NN Pilot and Andes compute libraries to map TinyML (Visual Wake Word / MLPerf Tiny) onto the RISC‑V vector… | ||
| Hands-on TinyML Deployment on RISC-V: Building an Optimized Edge AI Pipeline | RISC-V Summit Europe 2026 Developer Workshops | 2026-06-08 |
Hands-on workshop shows a full pipeline that converts TinyML models to tuned binaries and runs them on RISC-V hardware using an open RISC-V AI software stack… | ||
| Could RISC-V Become a Force in HPC? | RISC-V at embedded world 2024 | 2024-04-09 |
Claims a production-ready RISC-V stack: a 64-bit AX65 core (RV64GC) with 13-stage pipeline, up to eight cores, quad-issue and 128‑entry ROB, and an AX45MPV… | ||
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