RISC-V at embedded world 2024
2024-04-09..2024-04-11
Nuremberg, Germany
as the organisers put it
Sponsor view the 2024 agenda Thank you to all who joined us for RISC-V at Embedded World 2024! We look forward to seeing you at future events. To experience the best of this year’s event…
| title | author | length |
|---|---|---|
| Andes Interview | 04m | |
Andes reports being the leading RISC-V shipping company in Greater China, with deployed cores for consumer MCUs and MPUs, cites several US AI and HPC success… | ||
| BeagleBoard Interview | 03m | |
BeagleBoard shows production-ready RISC-V work: boards using Alibaba TH1520 and C910 silicon expose the implemented vector extension (the 71 vector spec… | ||
| MachineWare Interview | 05m | |
MachineWare updates Sim5 to add vector cryptography and cache management ops for early software work on the newest RISC-V extensions, and ships fast simulation… | ||
| Siemens Interview | 04m | |
Claims a silicon IP that implements the RISC‑V processor branch trace scheme, compresses on‑chip instruction traces enough to support simultaneous multi‑CPU… | ||
| Synopsys Interview | 02m | |
Synopsys presents concrete moves to support RISC‑V: it claims Arc 5 RISC‑V processor IP as a direct product extension, integrates a recent acquisition of a… | ||
| TiempoSecure Interview | 05m | |
TempoSecure rebrands as a premium security vendor, claims the embedded security market grows over 60% between 2019 and 2025, and points to rising attacks and… | ||
| RISC-V In Conversation | Calista Redmond, Kenneth Briodagh | 13m |
Membership grows more than 25% year over year to over 4,300 members and government adoption advances as the ministry of Brazil joined the board. RISC‑V moves… | ||
| RISC-V Revolutionizing in AI | Vince Wu | 10m |
Claims a market surge with 16 billion RISC-V chips by 2030 and AI accelerators taking the second-largest share, and presents Endis hardware and software… | ||
| Lightning Round | 11m | |
Quick briefs on concrete claims and demos: a CPU-IP vendor lists 30 RISC‑V cores, 400 commercial licenses, 580 staff with 80% R&D and 14 billion chips shipped… | ||
| Fast Virtual Platforms for Custom RISC-V Processors | Lukas Jünger, Zdenek Prikryl | 11m |
Claim: an end-to-end flow turns a single CODAL description into RTL, an LLVM-aware SDK, and a Sim5 plugin for MachineWare virtual platforms so teams can run… | ||
| Boosting AI on Semidynamics RISC-V Cores with Custom Tensor Instructions | Roger Espasa | 10m |
Proposal: a single RISC‑V element combining an out‑of‑order Atrio R5 core, an out‑of‑order vector unit supporting RVV 1.0 and a configurable tensor unit… | ||
| SiFive Development Tools | Dany Nativel | 10m |
Announces a HighFive Premier p550 board built around a 1.4 GHz quad‑core out‑of‑order R5 p550 and a removable system‑on‑module that carries LPDDR5/DDR5, eMMC… | ||
| OpenHW industrial grade, open source RISC-V Cores for EVERYONE | Florian Wohlrab | 16m |
OpenHW provides industrial RISC‑V cores under Apache-2 licensed cores with SystemVerilog implementations, UVM verification IP and FPGA images, claiming over… | ||
| Zero Trust Hardware Design for Embedded Systems | Florian Caullery | 10m |
Zero trust applied to embedded drones with concrete chips rather than theory: two RISC‑V SOCs are taped out — Shaheen as a small test chip and Alsaker taped… | ||
| ImperasFPM Fast Processor Models | Jon Taylor | 10m |
Imperas FPM uses JIT binary translation of RISC‑V to x86 and claims to boot Linux in seconds where RTL runs at kHz and takes days, and emulators/FPGAs take… | ||
| The Future of Embedded Security with RISC-V | David Kerr-Munslow | 09m |
A RISC-V based secure element is described that embeds countermeasures against side‑channel attacks inside the CPU, uses isolated encrypted memory with ECC… | ||
| RISC-V is Here! Innovation and Adoption Driving the Open Compute Future | Calista Redmond | 19m |
RISC-V International reports concrete milestones: 40+ technical specifications and 123 ratified extensions, an ecosystem over 4,300 members across 70… | ||
| Leveraging the RISC-V Efficient Trace (E-Trace) Standard | Devan Sharma | 10m |
Describes a compact encoding that reports start address and only branch outcomes and indirect targets so instruction flow is reconstructed without logging… | ||
| Could RISC-V Become a Force in HPC? | Niraj Dengale | 20m |
Claims a production-ready RISC-V stack: a 64-bit AX65 core (RV64GC) with 13-stage pipeline, up to eight cores, quad-issue and 128‑entry ROB, and an AX45MPV… | ||
| Early Code Coverage Analysis Using RISC-V Virtual Platforms | Lukas Jünger | 13m |
RISC-V virtual platforms produce non‑intrusive code coverage from full system simulation: a Sim5 simulator runs Zephyr with a TCP server, the test client sends… | ||
| Fast prototyping with RISC-V Microcontrollers | Giancarlo Parodi | 20m |
Renzas claims a ready-to-use RISC-V flow: a credit-card sized fast prototyping board with on-board SEGGER J-Link and virtual COM over USB-C, a 48 MHz MCU with… | ||
| Synopsys ARC-V™ Processor Family | Gordon Cooper | 10m |
Synopsys announces the ARCv5 RISC‑V processor family and claims to marry 25 years of processor IP with the RISC‑V ecosystem, shipping 3.5+ billion units… | ||
| Automotive Cybersecurity Makes Bounds in Building (RoT) | Frédéric Heitzmann | 07m |
Claims a working tesic secure Enclave built around an R5 CPU with lockstep for safety, configurable crypto accelerators (including an AES hardware accelerator… | ||
| BeagleV®: DRIVING RISC-V GROWTH | Jason Kridner | 07m |
Two BeagleV boards ship now for RISC‑V development: BeagleV Ahead is a 64‑bit quad‑core C910 (out‑of‑order, superscalar) running at 2 GHz with pre‑release 0.71… | ||
| Boost SoC Debug with Smart Monitors and Embedded Software | Devan Sharma | 11m |
Shows embedding a suite of RDL monitors (including a RISC‑V enhanced trace encoder offering cycle-accurate instruction trace) and using a bus monitor to… | ||
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