Early Code Coverage Analysis Using RISC-V Virtual Platforms
summary
RISC-V virtual platforms produce non‑intrusive code coverage from full system simulation: a Sim5 simulator runs Zephyr with a TCP server, the test client sends specific commands (G, M, H) and the platform records a trace file that the VP C tool converts into a standard coverage report. The demo shows uncovered code becoming covered after sending distinct inputs, runs entirely before hardware exists, and scales to thousands of parallel instances for CI integration.
AI-written summary · about
chapters (6)
- 0:00Introduction
- 2:13Software complexity challenges
- 3:57Code coverage analysis basics
- 6:01Demo setup overview
- 8:30Live coverage analysis demo
- 10:55Summary and benefits
related talks
13mEarly RISC-V Software Verification with SIM-V
17mDemo: RISC-V Models for Verification, Software Development and Architectural Explor...
09mExploring RISC-V architectures with VPSim, a virtual prototyping environment
13mIntroduction to RISC-V Processor Verification
11mRunning Quake on RISC V with Virtual Platforms
10mRISC-V Virtual Platforms for Early RISC-V Embedded Software Development
16mIntroduction to RISC-V Processor Verification
11mDemo: Accelerating SW Development and Validation of RISC-V Based Designs
