How to: Bringing up ExecuTorch on a RISC-V Microcontroller
summary
Shows how to port ExecuTorch (embedded PyTorch) to a new bare‑metal RISC‑V microcontroller by creating an ahead‑of‑time processor backend and adapting the ExecuTorch runtime. Covers delegating ops for custom RISC‑V ISA extensions, planning memory hierarchy and quantization delegation, and adding custom 8‑bit quantized operators using the PULP SIMD extension on a Verilator model of the OpenHW CV32E40Pv2 core. Finishes with notes on DMA/double buffering, bare‑metal multithreading and support for accelerators (e.g. GEMM), and applicability to other AI runtimes like TensorFlow Lite RT.
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