Empower Upstream ML Frameworks on RISC-V
summary
A system proxies upstream TensorFlow/PyTorch operator calls from a minimal RISC‑V stub to an accessible host that actually runs the heavy libraries and hardware, letting native apps run no code change and no framework install on the RISC‑V target. A host agent exports operator modules and PCIe accelerators (GPU/FPGA) via RPC while a backend graph compiler (e.g. TVM/OpenVINO style) JITs models for the accelerator; demos show x86+GPU→RISC‑V and arm64→RISC‑V inference working.
AI-written summary · about
chapters (7)
related talks
17mEmpower ML Framework on RISC-V by Backend Graph Compilers
19mBuilding Tool Chains for RISC-V AI Accelerators
34mBridging the Gap: Compiling and Optimizing Triton Kernels Onto RISC-V Targets Based on MLIR
45mThe Benefits of Building New AI Accelerators with RISC-V
10mAvoiding Amdahl's Law RISC-V Architecture Exploration for AI & ML Compute
40mHands-on TinyML Deployment on RISC-V: Building an Optimized Edge AI Pipeline
09mLightning Talk: RISC-V and AI: How an Open-Standards ISA Underpins Portability f...
10mLightning Talk: Software Development for ML and RISC-V Vector Acceler...