High-Performance RISC-V Processor for Computation Acceleration and Server

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" summary

Ascalon is a high-performance RISC-V core family aimed at AI and server workloads with an 8-wide decode O-o-O front end, large ROB, six integer ALUs, two floating-point pipelines and 2x256-bit vector units, built in RTL and progressing through physical design (PDGR die shown). Cores cluster with a 12 MB shared cache into a composable chiplet system forming a 128-core chiplet system and hierarchical ccNUMA fabric with 230 GB/s coherent fabric links; five derivatives are planned and the design is actively being validated.

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" chapters (19)

1. 0:00Introduction
2. 0:21Agenda
3. 1:00About the project
4. 2:22Why RISCV
5. 5:03Design Process
6. 6:35Performance Model
7. 8:01Design Methodology
8. 9:33ASCON Cluster
9. 10:57ASCON System Architecture
10. 12:12Product Overview
11. 13:35Product Architecture
12. 14:06Great School System
13. 14:47Wormhole Portal
14. 15:33CPU
15. 16:01AI computation
16. 18:59Machine learning
17. 19:50Data movement
18. 21:20Server
19. 22:27Summary

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