Industrial Strength High Performance RISC V Processors For Energy Efficient Computing
summary
Company emerges from stealth to describe a 7 nm strategy: a 16-core high‑single‑thread “Maxion” Linux SMP plus a tiled array of over 4,000 ET minion cores with per-core vector FPU, claiming multi‑teraflop on‑chip ML via a network-on-chip and high‑bandwidth DRAM. Design flow uses Verilog RTL and standard Cadence/Synopsys/Mentor flows starting from BOOM v2, simulating ResNet‑50 inference (batch 8) across the array and planning licensable cores and graphics shader support.
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chapters (11)
- 0:00Introduction and stealth mode
- 2:25RISC V high performance gap
- 6:59Esperanto's mission and cores
- 10:12Maxion high single-thread core
- 13:05ET Minion vector floating-point core
- 14:48AI supercomputer on a chip
- 17:20Machine learning performance demo
- 18:43Graphics on RISC V cores
- 20:14Proprietary ISA critique
- 21:41RISC V as better alternative
- 22:02Summary and licensing plans
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