Memory Consistency Model Status Update
summary
A RISC‑V memory model is released as an RVWMO base model for general software compatibility plus an optional ZTSO extension to expose stricter TSO semantics for legacy x86 or formally verified cores. The specification mandates multi-copy atomic visibility, clarifies LR/SC and atomics, adopts acquire/release semantics (deprecating load‑release/store‑acquire), marks AQRL as SC, and provides multiple formalizations and a public draft for toolchain and hardware validation.
AI-written summary · about
chapters (13)
- 0:00Introduction and goals
- 1:03Memory model definition
- 3:09Strong vs weak memory models
- 5:13Two proposed models
- 6:39Supporting both models
- 8:25Multi-copy atomicity concept
- 10:12RVWMO vs RVTSO differences
- 12:20Synchronization rules
- 13:43Software compatibility overview
- 15:51Hardware and software compatibility table
- 18:19Use case recommendations
- 20:06Fragmentation concerns
- 21:33Other changes and future work
related talks
32mMemory Model
01h 02mThe Two Memory Models
21mWeak Memory Demands Model-based Compiler Testing
01h 11mProgramming language memory models: Problems, solutions, and directions
16mModel Checking for a Multi-Execution Memory Model
28mCAAT: Consistency as a Theory
16mCompound Memory Models
22mExtending Intel-x86 Consistency and Persistency: Formalising the Semantics of In