Performance Isolation For Multicore Within Labeled RISC V

on YouTube ↗12m

" summary

Proposes a labeled microarchitecture called arena that conveys software identity to hardware via label registers propagated across cores and caches and enforced by label-indexed control tables and a new PRM resource manager. Implements changes in Rocket Chip and Chisel, adding under 3% extra code and under 5% control logic overhead. Demonstrates a label token bucket that restores memory-bandwidth-sensitive VM performance to solo levels and a label-based hypervisor path that removes VM-exit cache flush costs.

AI-written summary · about

" chapters (9)

1. 0:00Introduction
2. 0:18History of Control
3. 3:57Network Hardware
4. 4:32OMA Architecture
5. 5:23Label Architecture
6. 8:34Overheads
7. 9:10Label Height
8. 10:04Bandwidth Isolation
9. 10:44Conclusion

" related talks

• 15mCore slicing: closing the gap between leaky confidential VMs and bare-metal cloudAndrew Baumann, Ziqiao Zhou, Yizhou Shan, Marcus Peinado, Weidong Cui, Xinyang Ge · OSDI 2023
• 19mEnhancing RISC-V Embedded Processor Performance Through Advanced Instruction F...C. Basto, R. Ofir · RISC-V Summit North America 2025
• 28mSanctum: Minimal Hardware Extensions for Strong Software IsolationSrinivas Devadas, Victor Costan, Ilia Lebedev · USENIX Security '16
• 23mRISC V Enclaves A Clean Slate Approach To Linux SecurityCesare Garlati · RISC-V Summit 2019
• 20mArchitectural Extensions for a RISC V Processor for Embedded SecurityTariq Kurd · RISC-V Summit 2019
• 17mSecuring High-performance RISC V-Processors from Time SpeculationChris Celio · 8th RISC-V Workshop Barcelona 2018
• 21mAdaptable, Scalable and Predictable Computing with a Multi-threaded RISC-V Architectu...Henk Muller · RISC-V Summit 2022
• 20mLimitations and Opportunities of Modern Hardware Isolation MechanismsVikram Narayanan, Anton Burtsev, Xiangdong Chen, Zhaofeng Li, Tirth Jain · USENIX ATC 2024