Enhancing RISC-V Embedded Processor Performance Through Advanced Instruction F...
summary
Claims a microarchitectural fusion that gives dual‑issue class performance by increasing fetch bandwidth, augmenting the decoder and adding a third register read port while reusing existing function units and optionally multibanking memory. Implementation in the ARK5 RMX core uses physical synthesis to measure costs and shows 20% area increase and 25% IPC improvement on CoreMark (score ~6), with no ISA changes and compatibility with software that opts out of fusion, demonstrating linear complexity growth instead of quadratic.
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chapters (8)
- 0:00Introduction and motivation
- 3:18Performance challenges in embedded RISC-V
- 5:06Instruction fusion techniques
- 9:02Enhancing single-issue cores
- 13:40Dual-issue capabilities and examples
- 15:53Performance and area results
- 16:57Implementation matters and conclusion
- 17:41Q&A discussion
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