The Genius of the RISC-V Microprocessor

on YouTube ↗01h 01m

" summary

Claims that RISC-V is a tiny, modular ISA with 47 base instructions and optional named extensions (G, M, A, F, D, V) that let designers pay only for needed transistors. Demo uses the Cornell RISC-V simulator and cites a paper showing compressed instruction + macro-op fusion brings RISC-V micro-op counts close to x86/ARM. Compressed encoding costs about 400 gates. Concrete silicon: Rocket cores are ~half the die of an ARM Cortex‑A5 and about one quarter the price in the example; Esperanto ships a 28B‑transistor SoC with many small vector cores and achieves high throughput at <20W.

AI-written summary · about

" chapters (35)

1. 0:00Start
2. 4:21Modular Design
3. 4:35Incremental Instruction Sets
4. 5:01The Cost of Adding Instructions
5. 5:48Modular Instruction Sets
6. 6:53Complexity Costs Money
7. 9:26RISC-V Extensions
8. 12:41Contrast with x86 and ARM
9. 14:19Interface Instruction Set Architecture (ISA)
10. 15:07Where is RISC-V Used?
11. 16:29IoT - Internet of Things
12. 16:46HPC and Machine Learning
13. 18:22Cornell RISC-V Simulator
14. 20:03Registers
15. 22:21Register Aliases
16. 25:03Encoding of RISC-V Instructions
17. 26:13How a RISC Processor Executes an Instruction
18. 27:12Fetch-Step 1
19. 27:49Decode - Step 2
20. 28:20Execute - Step 3
21. 28:43Writeback-Step 4
22. 29:16Counter Program
23. 32:45Micro-Operations
24. 34:05Micro-Op And Control Unit Changes to the traditional CPU Instruction decoding
25. 34:54Superscalar Microprocessor
26. 37:19CISC Use of Micro-Ops
27. 38:34CISC Gets the Upper-hand With Micro-Ops?
28. 39:05Compressed Instructions
29. 41:03Macro-Operation Fusion
30. 42:18RISC-V Genius: Combine Compression and Fusion
31. 43:20ARM and RISC-V Comparison
32. 47:52Performing Macro Fusion
33. 48:51Can We Do Better?
34. 50:45Does it Pay Off?
35. 54:38post-permalink

" related talks

• 01h 01mThe Genius of RISC-V MicroprocessorsErik Engheim · ACCU 2022
• 21mRISC-V ISA & Foundation OverviewRick O'Connor · RISC-V Workshop Chennai 2018
• 21mA Comparative Analysis of RISC-V Architecture Based on the RISC-V SoC DV ExperienceMoonki Jang · RISC-V Summit North America 2023
• 13mDemo: RISC-V as an Enabler of Heterogeneous ComputeZdenek Prikryl · RISC-V Summit North America 2023
• 19mRISC V ISA & Foundation OverviewRick O'Conner · 8th RISC-V Workshop Barcelona 2018
• 11mGetting Started with RISC-V Custom InstructionsJon Taylor · embedded world 2023
• 01h 10mWhy RISC-V Through ISA Customization DemonstrationKeith Graham · RISC-V Summit North America 2023
• 18mRISC-V ISA: Understanding Limitations and Methods to Improve Code Density & PerformanceGnanasekar Rajakumar, Ravikumar Gaddam · RISC-V Workshop Chennai 2018