The Future of Ibex - A Production-grade, Open Source 32-bit RISC-V Core
summary
A production‑grade 32‑bit RISC‑V core used in multiple tape‑outs and shipping inside OpenTitan silicon that will protect Chromebooks and Google datacenter services, Ibex is moving from a PULP origin toward tighter mainstream adoption with an Apache 2 licensed open RTL, dual‑core lockstep configurations in EL Grey, and concrete post‑quantum use. Work includes formal unbounded proofs with academic partners, convergence work to merge a Microsoft CHERI fork back into mainline (CHERI needs register/layout changes), and upcoming features: code‑size compression, new bit‑manipulation extensions, AXI/TileLink bus support, and i‑cache pinning.
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chapters (9)
- 0:00Introduction and overview
- 1:46Open source silicon mission
- 3:11Open Titan and El Grey
- 4:58IBEX core features
- 6:44Cherry Ibex and memory safety
- 8:50Formal verification progress
- 9:53Future features and compression
- 12:40Community contributions and call to action
- 13:46Q&A session
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