RISC-V and Open Source Hardware Projects BoF
summary
RISC-V is a stable open ISA enabling both open and proprietary cores; actual open cores taped out include Rocket, BOOM, Ibex and SweRV and the Allwinner D1 ships an Alibaba T-Head core whose RTL is public. Google plus SkyWater open a 130 nm SkyWater PDK (90 nm next) and offer a free multi-project wafer (MPW) 40 projects run, while TinyTapeout and Zero to ASIC teach the toolchain. FPGA-friendly flows use Python-based Amaranth and chipflow-style services to simulate, verify and tape out silicon.
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chapters (6)
- 0:00Start
- 0:57What is different about RISC-V?
- 2:53RISC-V Developer Boards
- 6:12Alibaba T-Head open source RISC-V cores
- 8:39Open source silicon
- 21:29RISC-V open source cores
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