Open Source Processor IP for High Volume SoCs
summary
A nonprofit organization organizes commercial-quality open-source RISC-V cores as the CORE-V family and moves the PULP platform Rocket and Ariane implementations into its repos, with about 14 tape-outs to date and production use in the GAP8 shipping product and NXP’s Vega eval board. A cloud-based verification testbench runs on commercial CAD and open tools, with a formal verification plan underway and planned 2020 tape-outs. Governance includes NXP BlueSpec Silicon Labs and Alibaba and staffing uses a 1:4 engineer ratio of in-house to member contributors.
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chapters (25)
- 0:00Introduction
- 0:38Agenda
- 1:46Risk 5 Talks
- 2:42Modularity
- 5:21YSA
- 6:13Array
- 6:25Cost drivers
- 7:12Challenges
- 13:04Core 5 Family
- 13:47Risky Core
- 14:22Ariane Core
- 14:53Implementations
- 15:40Evil Board
- 16:15Board of Directors
- 17:06Verification Task Group
- 17:50Company
- 18:30Summary slide
- 19:47Open standards
- 20:40Licenses
- 21:43Formal Verification
- 22:13Formal Verification Strategy
- 24:50Question
- 25:30Tapeout
- 25:45QA
- 26:43Implementation Model
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