RISC-V without a Register File

on YouTube ↗03m

" summary

Removes the conventional RISC-V register file and maps registers into memory so the first bytes act like zero-page style register access; the prototype is a purely combinatorial RISC-V core that performs two memory reads for instruction operands then a writeback, with an arbiter and handshake ports to a memory subsystem. Formal checks run against the design and a tiny runtime cache of two or three recently used registers reduces the otherwise heavy memory traffic.

AI-written summary · about

" chapters (3)

1. 0:00Introduction
2. 1:21Handshaking
3. 2:14Conclusion

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