Initializing RISC-V A Guided Tour for ARM Developers
summary
RISC-V basics: 31 general-purpose registers plus x0 zero, two ISAs (RV32I/RV64I) and the common linux target rv64g with atomics and F/D floats. Development uses bearbox on QEMU/tinyemu and Vex cores; bearbox boots Linux from a RISC-V linux header (image offset ~4MB, image size ~2MB, header ver 0x2) and the JS tinyemu demo runs Doom. Practical gotchas: cache coherency differs by board (cheaper boards are noncoherent), requiring manual cache maintenance or OpenSBI firmware calls for DMA and hart startup; Beagle V support exists but the board was discontinued.
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chapters (27)
- 0:00Intro
- 0:39About Me #1
- 1:33Why do we develop for RISC-V?
- 2:45RISC-V Overview
- 5:04RISC-V: Timers
- 7:48RISC-V: code models
- 9:52RISC-V: Kernel Assembly
- 11:33RISC-V: our development platforms
- 12:47RISC-V: Barebox on qemu
- 13:45RISC-V Linux Header
- 16:25RISC-V: Barebox on Beaglev
- 17:17RISCV: HART(CPU) Bootup
- 20:24Peripherals
- 20:58A Primer on Cache Coherency
- 23:38Cache-Coherent Interconnects
- 24:42Device mastering the Bus
- 27:01Linux DMA Mappings
- 28:14DMA Mappings on ARM
- 29:59Cache Coherency on RISC-V
- 30:43Cache In-Coherency on RISC-V
- 31:14Allwinner Dl (CPU: Alibaba Xuan Tie C906)
- 33:12StarFive JH-7100 (CPU: SiFive U74)
- 37:16Privilege Modes
- 38:36trap-and-emulate
- 41:02Supervisor Binary Interface
- 43:42JH7100 Clock/Reset Handling
- 47:09Got you interested?
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