Building Open Hardware with Open Software
summary
Uses an open source FPGA flow (Yosys/trellis/nextpnr via litex) to synthesize Lattice ECP5 bitstreams for OrangeCrab and a larger ecp5 board and implements two soft RISC-V CPUs: vexriscv (32-bit, Spinal HDL) and rocket (64-bit, Chisel). Builds Linux images inside Yocto/meta-ptx-fpga and runs CI with Jenkins; LED blink and Linux boot for both cores work on some builds. Remaining issues: reproducible tool versions, litex upgrades breaking boots, multicore VexRiscv failing to start, and Scala/SBT core generation not integrated into Yocto.
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chapters (22)
- 0:00Intro
- 0:55About Me
- 3:34Expected Background Knowledge
- 5:58FPGA Use Cases
- 9:11Motivation
- 12:53Starting Question
- 15:22Hardware
- 17:45Does the toolchain work?
- 19:51Real World Example
- 22:21Rocket CPU
- 22:55Integration into System on a Chip
- 25:06Linux on LiteX Rocket!
- 28:18LiteX Internals
- 30:45Going further
- 33:03Yocto
- 38:01Continuous Integration
- 39:09Open Issues
- 41:04Pre-generated CPU Cores
- 42:06Comparability of Results
- 43:07Alternatives to LiteX
- 45:11Use Case for Linux on RISC-V in FPGA
- 46:11Next Steps
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