FPGA and open hardware
summary
Claims a fully open-source flow from Verilog to bitstream for the iCE40 family and shows it actually synthesizes and configures hardware, not just slides. Uses open tools (Yosys-style C++ tools) and a cheap FPGA board to light LEDs and run a tiny CPU. Demonstrates a NOT gate using one lookup table, cites historical Xilinx start with 85,000 transistors and a runnable RISC-V 32-bit soft CPU that fits on the same board and remembers its program.
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