Open-Source Tools for FPGA Development
summary
Shows a full open source flow for the iCE40 FPGA by synthesizing an 8-bit Gray counter that drives eight LEDs from an oscillator using yosys for synthesis, arachne-pnr for place-and-route, icepack to make the bitstream and iceprog to flash it; simulation uses Icarus/iverilog + vvp + GTKWave and timing via icetime. Claims the iCE40 flow is complete and reproducible, notes the $25 dev kit became unobtanium with a 29 week lead time, and explains vendor bitstream secrecy and heuristics block wider open toolchains.
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chapters (21)
- 0:00Introduction
- 0:36Outline
- 1:35FPGA
- 6:54Program FPGA
- 9:44Analysis Synthesis
- 11:20Icarus
- 12:23Odin
- 13:18Jason
- 16:41Arachnid
- 18:50assembler
- 20:10iSpec
- 20:56IceTerm
- 22:36Demo
- 23:53Pin Map
- 26:20Simulation Verification
- 28:17G HDL
- 30:20Test Bench
- 30:55Simulation
- 32:57Visualization
- 33:29Summary
- 34:53Questions
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