Tutorial: Why NAND Flash Breaks Down
summary
Describes how NAND flash cells store and change charge and why that leads to errors such as read-disturb, retention loss and bit flips. Covers mitigation techniques used in embedded systems (ECC, wear leveling, paired-page management and related strategies) and discusses expected future directions for NAND reliability.
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chapters (29)
- 0:00Start
- 0:36Flash storage technology
- 4:35NAND flash is cheap
- 7:18How flash works
- 8:52Back to basics The transistor
- 13:02A transistor with memory
- 16:42Combining cells in NAND
- 20:56Increasing density MultiLevel Cell (MLC)
- 25:05MLC pages are often interleaved
- 28:40Reading a cell
- 30:08Bypass the floating gate with higher voltage
- 31:46NAND structure is like CMOS NAND gate
- 32:40Reading a Multi Level Cell
- 33:46Lower page requires 2 reads
- 35:12Programming the floating gate: Fowler-Nordheim tunneling
- 37:51Inhibit programming to keep at 1
- 38:37Bypass non programmed wordlines
- 39:24Programming a cell
- 40:57Number of electrons is stochastically distributed
- 42:25Program MLC
- 43:53Upper page - Lower page
- 45:49Erasing the floating gate: Reverse F-N tunnelling
- 46:21Reverse the field by charging bulk
- 46:44Erasing a block
- 47:59How flash fails to work
- 48:34Bit flips
- 50:06Error Correcting Codes
- 54:16Working with ECC
- 56:08Hardware support for ECC
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