Being Friendly to Your Computer Hardware in Software Development
summary
Practical systems lose most potential of modern hardware because software ignores memory geometry and controllers: useful bus time is around 10% bus utilization while DRAM needs refresh every 64 ms and has minimum addressable rows often ~1 KB memory row, so crossing row boundaries costs an open/close cycle. Memory controllers schedule across banks, ranks and channels; HBM is wide but really eight 120‑bit channels (HBM as 8×120 channels). Techniques that matter: address-aware data layout, non‑temporal stores, ERMS-style bulk memory moves, and mapping code to platform fetch/decode widths.
AI-written summary · about
chapters (12)
- 0:00Intro
- 2:44Dynamic Memory
- 6:43DDR
- 20:11Advanced Topics
- 28:38Core and Uncore
- 33:16Processor
- 45:19Microcode
- 52:01Register Naming
- 53:31Execution Units
- 55:53Out of Order
- 57:38Memory Copy
- 59:57Summary
related talks
01h 11mPerformance engineering - being friendly to your hardware
30mMemory tiering
13mHW/SW design recommendations for 16kb devices
48mPersistent Memory Usage within Linux Environment
43mLive in a world with multiple memory types
24mConsolidating representations of the physical memory
45mEfficient Use of Modern x86-Compatible CPUs
38mMaximizing Heterogeneous Memory Bandwidth in Multi-Socket Systems