Performance engineering - being friendly to your hardware
summary
Shows how commodity hardware actually behaves: DRAM is a leaking capacitor array with ~tens of nanoseconds for row operations and one kilobyte row granularity, banks and ranks let DDR4 sustain 32 outstanding requests not infinite bandwidth, and misaligned access costs ~10 ns per row switch. x86 decoding is parallel pattern matching and end-to-end instruction latency is more like 20–30 cycle end-to-end latency. Practical case studies include vectorized memcpy and ClickHouse memcopy tradeoffs and when microcode helps or hurts.
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chapters (13)
- 0:00Introduction
- 1:49Memory as addressable array
- 10:20Memory hierarchy and granularity
- 17:48Memory bank parallelism
- 26:02Processor basics
- 36:44Parallel x86 decoding
- 44:11Code density and ISA
- 50:37Out-of-order execution
- 57:39Cache hierarchy limits
- 1:03:19Memory copy optimization
- 1:06:57Hashing benefits
- 1:08:02Benchmarking best practices
- 1:10:20Q&A
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