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summary
Project brings up a working OpenPOWER 64-bit toolflow on a laptop: boots a Power9 functional simulator, runs GCC/GDB cross-toolchain to inspect assembly and registers, converts a Chisel soft-core to Verilog, and completes synthesis/place‑and‑route and timing with an open toolchain. Uses Yosys/open_timer/qrouter/magic/netgen and produces power‑performance‑area numbers. An automated install script ties the flow together; an eight‑week effort yields reproducible builds and PP&A reports, validated on student test designs.
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chapters (7)
- 0:00Introduction to project
- 1:07OpenPOWER ISA overview
- 2:52Power9 functional simulator
- 6:41GNU cross-compilation toolchain
- 7:43ChiselSoC and ASIC flow
- 10:35Open source CAD tools
- 13:01Q&A session
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