Open Source Digital Design Tooling Updates

on YouTube ↗21m

" summary

CHIPS Alliance reports concrete tooling: an open SV Test suite runs SystemVerilog compliance across tools and shows most tests green; Verible supplies linting, formatting and a language server used in CI; a Yosys-based SystemVerilog synthesis flow plus an HDM (universal hardware data model) and Surelog/UHDM parsing enable elaboration-driven passes; RISC-V DV runs randomized instruction stress tests against golden models; custom GitHub runners on GCP let public repos trigger private proprietary-tool checks without leaking logs.

AI-written summary · about

" chapters (12)

1. 0:00Chips Alliance intro
2. 1:05Chips Alliance mission
3. 2:54Chips Alliance work groups
4. 4:19SystemVerilog tooling gap
5. 6:08Shloock parser and HDM
6. 7:13Verible tools
7. 9:45Verible GitHub Actions
8. 10:28Verible language server
9. 11:30RISC-V DV framework
10. 12:54GitHub Runners for CI
11. 15:00UVM support and events
12. 16:50Q&A

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