A reusable verification, emulation and validation flow for ASIC design
summary
A reusable flow lets verification, firmware and software teams run the same tests against RTL simulation, FPGA emulation and eventual silicon so most work finishes before tapeout. It uses cocotb testbenches driven by pytest, bitfiles built with F4PGA and CI on GitHub CI with a self hosted runner, supports parallelized coverage-driven tests (thousands if desired), and validates a TDC example where the same HAL and SPI/stream drivers work on simulator, FPGA and 2×2 cm reticle chips first time right.
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chapters (12)
- 0:00Start
- 0:31Typical setup
- 0:56Development life cycle
- 3:12Chip Design and Manufacturing Cost
- 5:31Emulation
- 7:23Firmware
- 7:55Example module
- 8:34Top configuration
- 8:56User experience
- 9:32How simulation works
- 10:45Test reports
- 10:58Coverage and Randomization
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