Automated, Simulation-Based Flow for Low-Cost FPGA-Accelerated Devices with Z...
summary
Shows a usable, automated flow that takes a visual hardware graph and produces device trees, builds Zephyr, and runs the result in Renode simulator with FPGA peripherals co‑simulated directly from Verilog/VHDL. Targets the PolarFire 4+1 RISC‑V SoC on BeagleV‑Fire (~$150), integrates with VS Code and VSD visual system designer, and feeds into CI that already covers ~470 platforms. Demo adds a new memory‑mapped UART (custom address and IRQ) and boots the Zephyr shell in simulation; flashing the bitstream to real hardware remains vendor‑specific but supported.
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chapters (10)
- 0:00Automated FPGA simulation flow
- 1:47Hardware-software gaps bridged
- 5:44PolarFire SoC FPGA fabric
- 11:27BeagleV Fire RISC-V FPGA
- 15:00Zephyr RTOS for FPGA
- 21:45Open-source FPGA entry tools
- 23:53Live demo in Renode
- 33:39Device trees for hardware
- 35:49Future FPGA software flows
- 37:58Q&A
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