V4L2 Video Decoder/Encoder Development Journey
summary
V4L2 video decoder/encoder driver work results in wave5 driver merged into mainline after about two years of work; development splits into studying the V4L2 spec, an FPGA-based PCI dummy-device for early bringup, then verification on a TI board. Race conditions are solved with threaded irq + kfifo queuing instead of heavy interrupt handlers. Validation uses gst-launch, GStreamer plugins, v4l2-compliance and fluster test suites plus checkpatch and device-tree bindings; the implementation runs on hardware and passes functional tests, while upstream contribution follows checkpatch and maintainer workflows.
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chapters (17)
- 0:00Introduction
- 3:12V4L2 I/O flow and buffers
- 8:56Decoder vs encoder I/O
- 9:20FPGA test environment
- 11:13V4L2 driver helper functions
- 14:01V4L2 callbacks and conditions
- 16:33Debugging V4L2 drivers
- 17:22TI board and device tree
- 20:33Race conditions and interrupts
- 23:10GStreamer and Fluster testing
- 26:27Error handling and buffer flags
- 29:00Kernel contribution process
- 34:48Submitting patches
- 36:10Q&A: V4L2, VAAPI, errors
- 38:18Q&A: Hardware design and compatibility
- 40:33Q&A: Control IDs and buffers
- 43:01Q&A: Resolution changes and performance
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