V4L2 Video Decoder/Encoder Development Journey
summary
Development covers V4L2 spec study, FPGA prototype and a dummy PCI device to exercise vb2/M2M paths, then TI board verification and upstreaming; result is wave5 driver merged to mainline. Implementation uses threaded IRQ + kfifo queuing to avoid interrupt races, VB2 helpers and M2M callbacks for queue handling, device tree bindings for hardware info, and DMA-SG/V4L2 memory types. Testing uses gst-launch and fluster tests plus v4l2-compliance. Upstream workflow relies on checkpatch, patch series and a roughly two years to upstream cadence.
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chapters (17)
- 0:00Introduction
- 3:12V4L2 I/O flow and buffers
- 8:56Decoder vs encoder I/O
- 9:20FPGA test environment
- 11:13V4L2 driver helper functions
- 14:01V4L2 callbacks and conditions
- 16:33Debugging V4L2 drivers
- 17:22TI board and device tree
- 20:33Race conditions and interrupts
- 23:10GStreamer and Fluster testing
- 26:27Error handling and buffer flags
- 29:00Kernel contribution process
- 34:48Submitting patches
- 36:10Q&A: V4L2, VAAPI, errors
- 38:18Q&A: Hardware design and compatibility
- 40:33Q&A: Control IDs and buffers
- 43:01Q&A: Resolution changes and performance
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