Debugging Heterogenous SoC Using OpenOCD
summary
OpenOCD runs self-hosted on A53 to debug R5 and M4 cores over the SoC fabric, removing the need for JTAG dongles; the patches are merged to mainline and work on TI AM625/TDA4VM and Beagle AI‑64. M4 uses direct AP access while R5 requires an emulated AP for R5 implementation, GDB multiarch connects over TCP, and the setup is fast and usable for Zephyr/freeRTOS workflows — caveats: /dev/mem permissions, watchdogs, and don’t debug the A53 from the same A53.
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chapters (18)
- 0:00OpenOCD for heterogeneous SoCs
- 3:15Standardizing MCU debugging
- 5:28Heterogeneous processor systems
- 8:15JTAG and CoreSight basics
- 10:24OpenOCD architecture
- 13:59Removing JTAG hardware
- 16:29Building OpenOCD for SoCs
- 19:37Debugging heterogeneous cores
- 21:43Remote debugging over sockets
- 23:27OpenOCD with dev tools
- 25:56Memory-based debugging benefits
- 26:18Debugging pitfalls
- 28:03Debug bypass and emulation
- 30:35OpenOCD memory mapping
- 33:27OpenOCD future directions
- 36:35RISC-V and UCI challenges
- 38:01Community resources
- 39:11Q&A
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