Look inside your SoC with Open SoC Debug
summary
Open SoC Debug is a full spec plus reference hardware and software stack that adds tracing, memory access and UART tunneling to SoCs, with working support for RISC‑V and OpenRISC cores and a rewritten host stack (the glib host library). It introduces subnets so multiple chips or FPGAs appear as one debuggable system, exposes register‑mapped control plus packetized trace/event streams, adds Python bindings and a UART emulation tunnel, and implements run‑control (GDB integration) in hardware/software; run‑control is very small while tracing costs more buffer resources.
AI-written summary · about
chapters (6)
- 0:00Start
- 0:23What Is Open Sock Debug All about
- 4:34Overview
- 7:09Debug Modules
- 9:37Chip Interface
- 17:04Uart Device Emulation
related talks
42mDebugging Heterogenous SoC Using OpenOCD
20mUltraSoC Presentation
16mEfficient debug and trace of RISC-V systems: a hardware/software co-design approach
16mA Unified Debug Server for Deeply Embedded Systems and GDB/LLDB
11mBoost SoC Debug with Smart Monitors and Embedded Software- 42mDebugging Heterogenous SoC Using OpenOCD
11mHeterogeneous Multicore Debugging of RISC-V Cores in Complex Chips
11mDemo: Heterogeneous Multicore Debugging of RISC-V Cores in Complex Chips