OSVVM: Methodology, Library, and Models
summary
Open Source VHDL Verification Methodology (OSVVM) is an open library for VHDL2008 simulators (GHDL, Mentor, Cadence, Synopsys work in progress) that delivers transaction-level modeling with records and resolution functions, constrained random stimulus via protected types, and built-in functional coverage and scoreboards. It includes transcripts/logging, synchronization primitives, memory models that cut a client’s simulation from 24h → 1h, and reusable AXI/UART models; the library is used successfully for FPGA and ASIC verification.
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chapters (13)
- 0:00Start
- 0:20What Is Os Vvm
- 7:48Randomization
- 8:09Weighted Distributions
- 10:36Functional Coverage
- 11:35Alu
- 19:20Logs
- 20:47Alerts
- 21:23Affirmations
- 22:04Report Alerts
- 22:44Scoreboards
- 23:35Member Modeling
- 25:19Synchronization Primitives
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