ORConf 2018
| title | author | length |
|---|---|---|
| Welcome and Update by the FOSSi Foundation | 08m | |
Seventh annual conference started in 2012 grows from 15 attendees to about 100 attendees this year with steady turnout; the foundation runs eva cost org as a… | ||
| RISC-V CPU Project in Western Digital | Zvonimir Z Bandić | 43m |
Western Digital develops a RISC-V core ECHX1 as a 2-way superscalar 9-stage pipeline implemented in TSMC 28 nm reaching ~970 MHz (target 1 GHz) and occupying… | ||
| Verilator 4.0 - Open Simulation Goes Multithreaded | Wilson Snyder | 30m |
Verilator 4.0 generates C++ from SystemVerilog-like RTL and adds multithreaded macro-task partitioning that groups many micro-tasks into ~10x macro tasks… | ||
| The nextpnr FOSS FPGA place-and-route tool | Clifford Wolf | 33m |
nextpnr is a retargetable FOSS place-and-route tool that replaces arachne-pnr for the iCE40 flow and already supports ice40 and ECP5 backends; it exposes a… | ||
| An update on SymbiFlow - a multiplatform FPGA project | Tim Ansell | 34m |
SymbiFlow positions itself as the gcc of FPGAs: an end-to-end, open-source flow from Verilog to bitstream. It uses Yosys for synthesis, Project… | ||
| Practical aspects of using the Open Source SCR1 core | Ekaterina Berezina | 15m |
SCR1 is an open‑source MCU‑class RISC‑V core (released under the Solderpad Hardware License) that implements RV32I/RV32E with optional M and C extensions… | ||
| Clash: Haskell as an HDL | Martijn Bastiaan | 27m |
Clash compiles Haskell to Verilog/VHDL and demonstrates that real hardware can be written as pure Haskell: a tiny parametric CPU is implemented (register count… | ||
| Another Introduction to Cocotb | Luke Darnell | 17m |
Hands-on introduction to cocotb showing Python-driven RTL verification against standard simulators (default: Icarus), VPI-based access to signals, and runnable… | ||
| Cocotb as a comprehensive verification platform | Marek Cieplucha | 21m |
Argues that functional verification is software and shows a working cocotb-based flow that adds constraint randomization and metric-driven verification to… | ||
| RISC-V ecosystem update | Michael Gielda | 25m |
RISC-V now runs 64-bit Linux in mainline Linux 4.19, has growing Zephyr support and active LLVM/GCC work, and playable FPGA hardware like the GreenWaves GAP8… | ||
| RISC-V & Renode: towards software-driven development | Michael Gielda | 22m |
Renode is an open-source framework that runs binary-compatible RISC-V and other SoC images, enabling multi-node simulation (demo: six virtual machines, HiFive… | ||
| Lessons learned while formally verifying the ZipCPU | Dan Gisselquist | 26m |
ZipCPU gets fully proven with SymbiYosys using induction and bounded checks, finding bugs tests never caught: bus reads that don’t halt, compressed-instruction… | ||
| Formal Verification of WARP-V, a TL-Verilog RISC-V Core Generator | Ákos Hadnagy | 18m |
The presentation will briefly outline the motivation and difficulties behind designing and verifying a flexible, easily configurable RISC-V based processor… | ||
| OpenRISC Update | Stafford Horne | 24m |
Maintains upstream ports for Linux, binutils, gdb and gcc and reports concrete progress: upstreamed Linux and newlib patches (about 20 newlib patches cleaned)… | ||
| Dockerizing your simulation/development environment | Gaspar Karm | 10m |
Shows how a full simulation/dev image is built and reused: installs GHDL, Cocotb and minimizes an Intel Quartus install, copies compiled Intel/Altera netlist… | ||
| Pyha: Python overlay for OOP-VHDL | Gaspar Karm | 19m |
Pyha converts object‑oriented Python straight into synthesizable VHDL by turning Python records into VHDL records/registers and translating the clock‑cycle… | ||
| Raising the level of abstraction in digital design with Chisel3 and FIRRTL | Jack Koenig | 26m |
A concrete workflow is described: Chisel3 programs generate FIRRTL which lowers to low FIRRTL for reusable compiler transforms, emitting Verilog for simulators… | ||
| OSVVM: Methodology, Library, and Models | Jim Lewis | 30m |
Open Source VHDL Verification Methodology (OSVVM) is an open library for VHDL2008 simulators (GHDL, Mentor, Cadence, Synopsys work in progress) that delivers… | ||
| Retargeting a legacy ISA CPU core to the RISC-V architecture | Krzysztof Marcinek | 12m |
The presentation will briefly describe the process of retargeting the proprietary 6-stage legacy ISA CPU core to RISC-V architecture. Two BSc students were… | ||
| SpinalHDL: Software generated hardware | Charles Papon | 27m |
SpinalHDL is a Scala-based DSL that emits synthesizable VHDL/Verilog netlists and runs as ordinary Scala code, not a separate compiler. It enforces explicit… | ||
| Python as a language for testing and code generation | Ben Reynwar | 19m |
Describes using Python to generate parameterised VHDL, run file‑based unit tests and drive FPGA validation, noting generation replaces unsupported VHDL… | ||
| Get into your own free LibreSilicon | Hagen Sankowski | 27m |
Project builds a free, open manufacturing flow: a 1µm process and a Standard Cell Library, using an open toolchain (qtflow) and a refurbished cleanroom in Hong… | ||
| Find better cores with LibreCores | Philipp Wagner | 20m |
A community site that aggregates IP cores and project metadata from GitHub and shows code activity graphs now adds a hierarchical classification, autocomplete… | ||
| Look inside your SoC with Open SoC Debug | Philipp Wagner | 27m |
Open SoC Debug is a full spec plus reference hardware and software stack that adds tracing, memory access and UART tunneling to SoCs, with working support for… | ||
| Open Supply Chains - the Quattro S Initiative | Arnd Weber | 21m |
The Quattro S initiative claims it can make the entire IT value chain transparent and secure by combining Security, Safety, Sovereignty and Social Product… | ||
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