Ekaterina Berezina
where else to find them
no profile links on file
what they talk about
where they keep going back
- ORConf2 editions2018–2019
on a stage with
all 38 in the filters
who talks about the same things
- Drew Fustini21 talks
- Stephano Cetola6 talks
- Alistair Francis10 talks
- Calista Redmond37 talks
- Olof Kindgren14 talks
- Rick O'Connor25 talks
| title | conference | date |
|---|---|---|
| Open Source SCR1 core | ORConf 2019 | 2019-09-27 |
SCR1 is an open-source MCU-class RISC-V core that ships on GitHub with configurable RTL, QuickStart guides, tests and simulation scripts and an SDK repository… | ||
| Practical aspects of using the Open Source SCR1 core | ORConf 2018 | 2018-09-21 |
SCR1 is an open‑source MCU‑class RISC‑V core (released under the Solderpad Hardware License) that implements RV32I/RV32E with optional M and C extensions… | ||
| Poster / Demo Previews | 8th RISC-V Workshop Barcelona 2018 | 2018-05-07 |
Poster session previews list concrete results and demos to see: a quantum‑resistant secure boot shows large speedups on HiFive hardware; CGEN generates… | ||
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