Alistair Francis
where else to find them
no profile links on file
what they talk about
all 6 in the filters
where they keep going back
- linux.conf.au2 editions2020–2021
all 7 in the filters
on a stage with
- Hugh Blemings2×
- Anup Patelonce
who talks about the same things
- Stephano Cetola6 talks
- Drew Fustini21 talks
- Ben Dooks12 talks
- Atish Patra17 talks
- Calista Redmond37 talks
- Rouven Czerwinski8 talks
| title | conference | date |
|---|---|---|
| Writing an Embedded Operating System in Rust | Embedded IoT Summit @ Open Source Summit Europe 2022 | 2022-09-13 |
Claims a complete embedded OS written in Rust called Tock OS runs on ARM Cortex-M and RISC‑V hardware, uses Rust safety for untrusted code and RISC‑V PMP / ARM… | ||
| Mainlining the reMarkable 2 eInk tablet | FOSDEM 2022 | 2022-02-05 |
The reMarkable 2 is an eInk tablet, based on the i.MX7 SoC. The tablet
ships with a fork of the 4.14 kernel and a custom rootFS built with
OpenEmbedded. The… | ||
| Using PMP, ePMP and Rust to Protect Embedded Kernels, Even from Themselves | RISC-V Forum: Security 2021 | 2021-04-14 |
Demonstrates that Tock OS uses RISC-V PMP write-xor-execute to mark kernel stack/data non-executable and kernel text read-only, and that ePMP default-deny adds… | ||
| Open ISAs (RISC-V, OpenPOWER, etc) | linux.conf.au 2021 | 2021-01-23 |
RISC-V and OpenPOWER move from experiments to deployable stacks: RISC-V toolchains and distros (GCC/LLVM, glibc, Debian/Fedora) now boot on QEMU and silicon… | ||
| Where Is the 32-Bit Glibc Port? | RISC-V Global Forum 2020 | 2020-09-03 |
Upstream glibc is adding 64-bit time_t on RV32, making RISC‑V the first 32‑bit architecture with y2038 safety, but it only works with requires Linux 5.4+… | ||
| RISC-V 32-bit glibc port | linux.conf.au 2020 | 2020-01-13 |
Adds 64-bit time_t on RV32 so RISC‑V 32‑bit can avoid the 2038 overflow, implements the new 5.1+ year‑2038‑safe syscalls and reworks glibc syscall wrappers… | ||
| OpenISA Miniconf Introduction | linux.conf.au 2020 | 2020-01-13 |
High-level orientation to two open ISAs with concrete details: RISC‑V is a small base ISA plus modular extensions (M, A, F, D, G, C) and Linux typically… | ||
| RISC V Hypervisor Support | RISC-V Summit 2019 | 2019-12-09 |
RISC-V hypervisor support is at v0.5 draft with QEMU patches adding 32- and 64-bit hypervisor/guest paths; the design uses a two-stage MMU and new H/VS CSRs so… | ||
| Developing the RISC-V Hypervisor Extensions in QEMU | Open Source Summit Europe + Embedded Linux Conference Europe 2019 | 2019-10-28 |
QEMU gains working support for the RISC-V hypervisor extension: full CSR handling including complex register swapping, RISC-V hypervisor CSRs and guest-visible… | ||
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