~/talks

Anup Patel

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titleconferencedate
SBI V3.0: Fueling the Next Wave of RISC-V System Software InnovationRISC-V Summit North America 20252025-10-22
SBI v3.0 specifies concrete extensions: SSE preemptive events that inject RAS notifications and PMU-overflow samples even with interrupts disabled, MPXY…
Talk
Demo: Nested Virtualization AccelerationRISC-V Summit North America 20232023-11-06
Demonstrates a working SBI 2.0 NACL extension implementation that uses a shared memory per vCPU to offload H-extension emulation, running xvisor as L0 with KVM…
Talk on
The SBI V2.0 and BeyondRISC-V Summit North America 20232023-11-06
SBI v2.0 finishes public review and targets ratification by year end, adding concrete extensions: power management (HSM, system suspend, CVPC) to coordinate…
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RISC-V Nested VirtualizationRISC-V Summit 20222022-12-13
Claims a working nested-virtualization stack for RISC-V that traps and emulates H-extension to run L2 VMs; proof-of-concept runs QEMU + Xvisor + KVM with a…
Talk on
AIA Virtualization in KVM RISC-VKVM Forum 20222022-09-12
Implements RISC-V Advanced Interrupt Architecture virtualization inside KVM with a working proof‑of‑concept on QEMU, OpenSBI, Linux KVM and kvmtool. Key…
Talk on
Perf on RISC-V: The Past, the Present and the FutureOpen Source Summit + Embedded Linux Conference + OSPOCon 20212021-09-27
Linux perf on RISC-V now moves from “cycles and instructions only” to full PMU support: an SBI PMU extension plus an ISA PMU feature add supervisor-accessible…
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OpenSBI Domain SupportRISC-V Forum: Security 20212021-04-14
OpenSBI adds domain support in v0.9 to provide system-level partitioning by using RISC-V physical memory protection (PMP) and a domain model that can extend to…
Talk on
Co-developing RISC-V Hypervisor Supportlinux.conf.au 20202020-01-13
Anup Patel https://lca2020.linux.org.au/schedule/presentation/204/ The RISC-V Hypervisor Extension Specification and RISC-V Hypervisor Software are being…
Talk on
RISC V Hypervisor SupportRISC-V Summit 20192019-12-09
RISC-V hypervisor support is at v0.5 draft with QEMU patches adding 32- and 64-bit hypervisor/guest paths; the design uses a two-stage MMU and new H/VS CSRs so…
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An Introduction to RISC V Boot FlowRISC-V Summit 20192019-12-09
Explains how Linux boots on RISC‑V by combining a ROM/FSBL, an openSBI runtime (mandatory for SBI calls like timer and TLB ops), U‑Boot (or direct kernel…
Talk on
Xvisor: Embedded Hypervisor for RISC-VOpen Source Summit Europe + Embedded Linux Conference Europe 20192019-10-28
Xvisor: Embedded Hypervisor for RISC-V - Anup Patel, Western Digital Xvisor is an open-source type-1 monolithic hypervisor. It is primarily designed and…
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