Perf on RISC-V: The Past, the Present and the Future
summary
Linux perf on RISC-V now moves from “cycles and instructions only” to full PMU support: an SBI PMU extension plus an ISA PMU feature add supervisor-accessible control, 29 programmable counters and an overflow interrupt bit, with bit 13 reserved for overflow and a 32-bit shadow CSR reporting which counters overflowed. OpenSBI implements the firmware interface, QEMU gains configurable HPM count width (default 16 programmable counters) and read/write CSRs, and a new perf driver in kernel 5.14 demonstrates counting, sampling and firmware-event support.
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chapters (18)
- 0:00Introduction
- 0:36Agenda
- 1:09Overview
- 3:00Current Status
- 4:10Specification
- 6:42Supervisor Mode
- 9:28PMF Extension
- 15:23SMP Extension
- 16:38Events
- 18:08Functions
- 19:18Flags
- 20:49Perf Implementation
- 22:24Linux Perf Implementation
- 22:42Driver Puff
- 24:57OpenSBI
- 27:33Scheme Implementation
- 28:21Current Implementation
- 29:34Future Work
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