I3C in Tomorrow's Design
summary
A two-wire bus that boosts I2C-style designs to 12.5 MHz SDR (DDR/TSP modes and optional 2–4 data lanes for higher throughput), using a 48-bit provisional ID and a dynamic address assignment (DAA) procedure to avoid address collisions, plus inbound interrupts, hot-join and controller-handover flows and a 14-transition reset pattern. Linux implements an i3c framework with device APIs and drivers—three controller drivers and one device driver upstream—but HDR and most v1.1 features (time sync, resets, HDR-BT) remain unimplemented.
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chapters (14)
- 0:00Start
- 4:37Backward compatibility with 12C
- 6:25Achieving higher frequencies
- 8:50Pure 13C frequencies
- 11:42Bandwidth: mixed modes
- 14:54Enhanced bus management
- 16:42Common Command Codes (COC)
- 25:59Controller handover
- 27:25Time synchronization (13C v1.1)
- 35:52The 13C bus infrastructure
- 36:51The 13C controller structure
- 37:50The 13C controller interface
- 38:24Additional information about bus initialization
- 40:25An 13C device driver
