Shared Virtual Addressing for High Performance Arm Infrastructure Platforms

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" summary

Design shows a working SVA implementation that lets PCI accelerators DMA guest or host virtual pointers by programming CPU page tables into the IOMMU and handling IO page faults across VFIO and virtio rings. Hardware pieces are SMMUv3 ATS/PRI/PASID support and PCIe devices; software pieces are KVM/VFIO, a back-end virtio IOMMU, and guest front-end handling nested page faults. Flow is validated end-to-end: ATS fails, PRI/PRI-queue invokes kernel page fault, guest updates PTs, virtio sends successful PRI response.

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" chapters (10)

1. 0:00Introduction
2. 0:19Outline
3. 0:59Why Virtual Addressing
4. 6:27Advantages
5. 8:03Hardware Requirements
6. 13:10VA Flow
7. 19:40Virtualization
8. 23:51Current Proposed Design
9. 26:05Virtual Machine Flow
10. 33:50Current Status

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